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module decoder( ADDR, ALE, CS_PLD,
SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS );input [2:0] ADDR;
input ALE, CS_PLD;
output SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS;wire [2:0] ADDR;
wire ALE, CS_PLD;
wire SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS;
reg [4:0] xCS; // так короче//----------------------------------------
assign SOC_CS = xCS[0];
assign CLK_CS = xCS[1];
assign OE_CS = xCS[2];
assign DIV_MCLK_CS = xCS[3];
assign DIV_CS = xCS[4];
always @(posedge ALE or posedge CS_PLD)
begin
if (CS_PLD) xCS <= 5'b11111;
else
begin
case (ADDR)
1: xCS <= 5'b11110;
2: xCS <= 5'b11101;
3: xCS <= 5'b11011;
4: xCS <= 5'b10111;
5: xCS <= 5'b01111;
default : xCS <= 5'b11111;
endcase
end
endendmodule
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