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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
Port ( clock : in std_logic;
bin3 : in std_logic;
fwr : in std_logic;
d : inout std_logic_vector (7 downto 0);
bout3 : out std_logic);
end main;
architecture Behavioral of main is
signal tmp_out : std_logic;
begin
process (clock)
begin
if( clock'event and clock = '1' ) then
bout3 <= bin3;
end if;
end process;
process (clock)
begin
if( clock = '1' ) then
if( fwr = '0' ) then
d <= "10101010";
end if;
end if;
end process;
end Behavioral;
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