[an error occurred while processing this directive]
|
module rom(clk, adr, dout);
input clk;
input [6:0] adr;
output [7:0] dout;
reg [7:0] dout;
always @(posedge clk)
case(adr)
7'h00: dout <= #1 8'h01;
7'h01: dout <= #1 8'h02;
7'h02: dout <= #1 8'h03;
7'h03: dout <= #1 8'h04;
default: dout <= #1 8'd00;
endcase
endmodule
E-mail: info@telesys.ru