[an error occurred while processing this directive]
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input [2:0] addr ;
wire [2:0] addr ;
output [7:0] d_out ;
wire [7:0] d_out ;
reg [7:0] mem [7:0];
initial begin
mem[0] = 4; mem[1] = 5; mem[2] = 6; mem[3] = 7;
mem[4] = 0; mem[5] = 1; mem[6] = 2; mem[7] = 3;
end
assign d_out = mem[addr];
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