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function get_slice (
arrval : std_logic_vector;
constant length : integer)
return std_logic_vector is
variable r : std_logic_vector(length-1 downto 0);
begin -- slice
for i in 0 to length-1 loop
r(i):=arrval(i);
end loop;
return r;
end get_slice;
constant max_width : integer :=cfg_filter(TAPS).WIDTH;
type interconnect is array (0 to TAPS) of std_logic_vector(max_width-1 downto 0);
signal wire : interconnect;
begin -- RTL
I_chanel: for j in 1 to TAPS generate
mf_inst: mf
generic map (
cfg_word => CFG_FILTER(j),
MAX_WIDTH => max_width
)
port map (
clk => clk,
in_sample => I_sample,
in_stream => get_slice(wire(j-1),CFG_FILTER(j).WIDTH),
out_stream => wire(j));
end generate I_chanel;wire(0)<=sxt(I_sample,max_width);
I_res<=wire(TAPS);
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