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//Ìîäóëü çàùèòû îò äðåáåçãà 12-òè èìïóëüñíûõ âõîäîâ ñ èçìåíÿåìûì ïåðèîäîì çàùèòû
module DREBEZG (START, CS, CLK, WR, AL, AD, IN, O);
input START; wire START;
input CS; wire CS; //Âûáîð öèôðîâûõ êàíàëîâ
input CLK; wire CLK; //Òàêòîâàÿ ÷àñòîòà 1 êÃö
input WR; wire WR; //ÑÈãíàë çàïèñè ïðîöåññîðà
input [6:0] AL; wire [6:0] AL; //Øèíà àäðåñà ïðîöåññîðà
input [7:0] AD; wire [7:0] AD; //Øèíà àäðåñà/äàííûõ ïðîöåññîðà
input [11:0] IN; wire [11:0] IN; //Âõîäû ñ öèôðîâûõ äàò÷èêîâ
output [11:0] O; wire [11:0] O; //Âûõîäû ïîñëå çàöèòû îò äðåáåçãàreg [7:0] MA, MB, MC, MD, ME, MF, MG, MH, MJ, MK, ML, MM;
PRO mod1 (CLK, IN[0], MA, O[0]); //Çàùèòà îò äðåáåçãà 1-ãî êàíàëà
PRO mod2 (CLK, IN[1], MB, O[1]); //Çàùèòà îò äðåáåçãà 2-ãî êàíàëà
PRO mod3 (CLK, IN[2], MC, O[2]); //Çàùèòà îò äðåáåçãà 3-ãî êàíàëà
PRO mod4 (CLK, IN[3], MD, O[3]); //Çàùèòà îò äðåáåçãà 4-ãî êàíàëà
PRO mod5 (CLK, IN[4], ME, O[4]); //Çàùèòà îò äðåáåçãà 5-ãî êàíàëà
PRO mod6 (CLK, IN[5], MF, O[5]); //Çàùèòà îò äðåáåçãà 6-ãî êàíàëà
PRO mod7 (CLK, IN[6], MG, O[6]); //Çàùèòà îò äðåáåçãà 7-ãî êàíàëà
PRO mod8 (CLK, IN[7], MH, O[7]); //Çàùèòà îò äðåáåçãà 8-ãî êàíàëà
PRO mod9 (CLK, IN[8], MJ, O[8]); //Çàùèòà îò äðåáåçãà 9-ãî êàíàëà
PRO mod10 (CLK, IN[9], MK, O[9]); //Çàùèòà îò äðåáåçãà 10-ãî êàíàëà
PRO mod11 (CLK, IN[10], ML, O[10]); //Çàùèòà îò äðåáåçãà 11-ãî êàíàëà
PRO mod12 (CLK, IN[11], MM, O[11]); //Çàùèòà îò äðåáåçãà 12-ãî êàíàëà//Ñîõðàíåíèå äëèòåëüíîñòè èíòåðâàëà çàùèòû îò äðåáåçãà
always @(posedge WR or negedge START)
if (!START)
begin
MA = 8'b11111111;
MB = 8'b11111111;
MC = 8'b11111111;
MD = 8'b11111111;
ME = 8'b11111111;
MF = 8'b11111111;
MG = 8'b11111111;
MH = 8'b11111111;
MJ = 8'b11111111;
MK = 8'b11111111;
ML = 8'b11111111;
MM = 8'b11111111;
end //if
else if (CS)
begin
if (AL == 60) MA = AD;
else if (AL == 61) MB = AD;
else if (AL == 62) MC = AD;
else if (AL == 63) MD = AD;
else if (AL == 64) ME = AD;
else if (AL == 65) MF = AD;
else if (AL == 66) MG = AD;
else if (AL == 67) MH = AD;
else if (AL == 68) MJ = AD;
else if (AL == 69) MK = AD;
else if (AL == 70) ML = AD;
else if (AL == 71) MM = AD;
end //else if
endmodule //DREBEZG
//********************************************************//Çàùèòà îò äðåáåçãà
module PRO (CLK, I, MOD, OUT);
input CLK; wire CLK; //Òàêòîâàÿ ÷àñòîòà 1 êÃö
input I; wire I;
input [7:0] MOD; wire [7:0] MOD;
output OUT; reg OUT;reg [7:0] A;
reg O;
reg X; //Ïåðåõîä îò 0 ê 1
reg Y; //Ïåðåõîä îò 1 ê 0
reg TIME;
//8-ìè ðàçðÿäíûé ñ÷åò÷èê ïî çàãðóæàåìîìó ìîäóëþ
always @(posedge CLK)
begin
if (A == MOD)
begin
A = 0;
TIME = 1'b1;
end //if
else
begin
A = A +1;
TIME = 1'b0;
end //else
end //always
//Êîíòðîëü ïåðåõîäà îò 0 ê 1
always @(negedge TIME or negedge I)
if (!I) X = 1'b0;
else X = 1'b1;
//Êîíòðîëü ïåðåõîäà îò 1 ê 0
always @(negedge TIME or posedge I)
if (I) Y = 1'b0;
else Y = 1'b1;
//Ôîðìèðîâàíèå çàùèùåííîãî îò äðåáåçãà ñèãíàëà (ïðè MOD > 0)
always @(posedge TIME)
if (X) O = 1'b1;
else if (Y) O = 1'b0;
//Ôîðìèðîâàíèå âûõîäíîãî ñèãíàëà
always @(MOD)
if (MOD == 0) OUT = I;
else OUT = O;
endmodule //PRO
P.S. Вы специально убрали кусок кода?
Как на мой взгляд, это не совсем хорошая реализация.
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