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library ieee;
use ieee.std_logic_1164.all;
entity buf2 is
port (
a: inout std_logic; -- Port A
b: inout std_logic; -- Port B
g_a: in std_logic -- Enable
);
end buf2;
architecture buf2_1 of buf2 is
signal start: boolean:=false;
begin
process begin
wait for 200 ns;
start<=true;
wait;
end process;
process( a, b, g_a, start ) begin
if( To_X01(g_a)='1' or start=false ) then
a<='Z' after 5 ns; b<='Z' after 5 ns;
elsif( falling_edge( g_a ) or start'event ) then
if( (a='1' and b='0') or (a='0' and b='1') ) then
a<='X'; b<='X';
elsif( (a='1' or a='0') and ( b/='1' and b/='0' ) ) then
b<=a after 6 ns;
elsif( (b='1' or b='0') and ( a/='1' and a/='0' ) ) then
a<=b after 6 ns;
end if;
else
if( a'event and a/=b ) then
b<=a after 0.25 ns;
elsif( b'event and a/=b ) then
a<=b after 0.25 ns;
end if;
end if;
end process;
end buf2_1;
library ieee;
use ieee.std_logic_1164.all;
entity pi5c3245 is
generic( name: in string:="BUF8" );
port (
a: inout std_logic_vector( 7 downto 0 ); -- Port A
b: inout std_logic_vector( 7 downto 0 ); -- Port B
g_a: in std_logic -- Enable
);
end pi5c3245;
architecture pi5c3245_1 of pi5c3245 is
component buf2 is
port (
a: inout std_logic; -- Port A
b: inout std_logic; -- Port B
g_a: in std_logic -- Enable
);
end component;
begin
D0: buf2 port map( a(0), b(0), g_a );
D1: buf2 port map( a(1), b(1), g_a );
D2: buf2 port map( a(2), b(2), g_a );
D3: buf2 port map( a(3), b(3), g_a );
D4: buf2 port map( a(4), b(4), g_a );
D5: buf2 port map( a(5), b(5), g_a );
D6: buf2 port map( a(6), b(6), g_a );
D7: buf2 port map( a(7), b(7), g_a );
end pi5c3245_1;
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