Отправлено 6 02 марта 2004 г. 19:05

А точнее процесс синтеза проходит, на выходе только Warning-и типа:
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:647 - Input is never used.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_NUMERIC_STD.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity corr1 is
Port ( S1 : in std_logic;
S2 : in std_logic;
CLK : in std_logic;
R : out std_logic_vector(0 to 9));
end corr1;

architecture Behavioral of corr1 is
signal Q_S1 : std_logic_vector(0 to 62);
signal Q_S2 : std_logic_vector(0 to 62);
signal BUF_S1 : std_logic_vector(0 to 30);
signal BUF_S2 : std_logic_vector(0 to 30);
signal xor_s : std_logic_vector(0 to 62);

begin
--Q_S1 <= (others => '0');
--Q_S2 <= (others => '0');

reg: process (S1,S2,CLK)
begin
--wait on CLK, RESET;
--wait until CLK'event and CLK='1';
if (CLK'event and CLK='1') then
case S1 is
when '1' =>
BUF_S1 <= (others => '1');
Q_S1 <= BUF_S1 & '1' & Q_S1(32 to 62);
when others =>
BUF_S1 <= (others => '0');
Q_S1 <= BUF_S1 & '0' & Q_S1(32 to 62);
end case;
case S2 is
when '1' =>
BUF_S2 <= (others => '1');
Q_S2 <= Q_S2(0 to 30) & BUF_S2;
when others =>
BUF_S2 <= (others => '0');
Q_S2 <= Q_S2(0 to 30) & BUF_S2;
end case;

end if;

end process reg;

XOR_S <= not (Q_S1 xor Q_S2);

--R(0) <= Q_S1;
--R(1) <= Q_S2;
end Behavioral;

Премного благодарен за внимание...

• Ответ: Sorry, здесь вернее... — 6   (02.03.2004 19:08, 1894 байт)
  • А какой сигнал то? — zlyh   (02.03.2004 20:12, 63 байт)
• Ответ: Sorry, здесь вернее... — 6   (02.03.2004 19:07, пустое)
  • Ответ: Вопрос снят, голова под конец рабочего дня совсем не варит... — 6   (02.03.2004 20:06, пустое)