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Он весь должен быть описан "под CLK".
process(clk2)
variable cnt : std_logic_vector (3 downto 0);
begin
if rising_edge(CLK2) then
FSR <= CLK_8 and not(cnt(3));
if CLK_8 = '0' then
cnt := (others => '0');
elsif cnt(3) = '0' then
cnt := cnt + 1;
end if;
end if;
end process;
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