Отправлено Карпинский Богдан 10 марта 2004 г. 21:12 В ответ на: ну вот отправлено yes 02 марта 2004 г. 15:51

-- file "LFSR8" compare by Karpinskij Bohdan
-- kDaniu@yandex.ru, kbz@tane.edu.ua
-- ширину шини даних можна міняти (добавити generic)

library IEEE;
use IEEE.std_logic_1164.all;
entity LFSR8 is
port (
CLK: in STD_LOGIC;
Enable: in STD_LOGIC;
Data: in STD_LOGIC_VECTOR (7 downto 0);
Mode: in STD_LOGIC_VECTOR (1 downto 0);
Result: out STD_LOGIC
);
end LFSR8;

architecture LFSR8 of LFSR8 is

begin
process (CLK)
variable Reg: STD_LOGIC_VECTOR (7 downto 0);
variable Pol: STD_LOGIC_VECTOR (7 downto 0);
variable current_value: STD_LOGIC;
begin
if CLK = '1' and CLK'event then --compare signal CLK
if Enable = '1' then --compare signal Enable
case Mode is
--load feedback polinom 'Pol'
when "00" => Pol := Data;
--load first state of shift register 'Reg'
when "01" => Reg := Data;
--Generate Quasi_Random Bits
when others =>
current_value := '1';
for A in 7 downto 1 loop --counter new bit and shift
if (Pol (A) = '1') then
current_value := current_value xor Reg (A);
end if;
Reg (A) := Reg (A-1);
end loop;
if Pol (0) = '1' then
current_value := current_value xor Reg (0);
end if;
Reg(0) := current_value;
-- send result
Result <= current_value;
end case;
end if; --for if Enable = '1' then
end if; --for if CLK = '1' and CLK'event then
end process;
end LFSR8;