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module rand ( rst, clk, do );
input rst, clk ;
output wire [31:0] do ;
parameter mask = 32'h82608edb;// ïîëèíîì
reg [31:0] sh_reg ;// -- ñäâèãîâûé ðåãèñòð
reg p ;//òðèããåð-çàùåëêà
wire [31:0] back ; // îáðàòíàÿ ñâÿçü
wire [31:0] smsk ;// âûõîä ìóëòèïëåêñîðà
wire [31:0] shft ; // ñäâèíóòûé ðåãèñòð
assign smsk = (p==1) ? mask : 0 ; // ìóëüòèïëåêñîð
assign shft[31:0] = {sh_reg[30:0], 1'b0} ; // ñäâèã ðåãèñòðà
assign back = smsk^shft; // ïîëíûé ñèãíàë îáðàòíîé ñâÿçè
//
//
//--Òóò ñèíòåçèðóåòñÿ òðèãåð-çàùåëêà è ñèíòåçàòîð ìîæåò âûäàâàòü
//--ïðåäóïðåæäåíèÿ, êîòîðûå íàäî õåðèòü, èáî òàê îíî è çàäóìàíî.
always @(rst or clk) casex ({rst,clk})//óïðàâëåíèå áèòîì p
2'b 1x : p <= 1 ; // 1 ïðè ñáðîñå (â ïðèíöèïå ìîæíî ïîõåðèòü)
2'b 00 : p <= sh_reg[31] ; endcase// ïðè êëîêå = 0 ïèøåì òóäà reg(31)
always@(posedge clk or posedge rst) // óïðàâëåíèå ñäâèãîâûì ðåãèñòðîì.
if (rst) sh_reg <= 32'hffffffff ; //--Ïðè ñáðîñå ïèøåì 0xffffffff èëè ëþáîå äðóãîå çíà÷åíèå, íå ðàâíîå 0
else sh_reg <= back ; //-- ïî ôðîíòó êëîêà ïèøåì â ðåãèñòð ñèãíàë îáðàòíîé ñâÿçè.
assign do = sh_reg ;// ïîäàåì çíà÷åíèå ðåãèñòðà íà âûõîä
endmodule
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