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// Module test
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST
module test(
RST_IN,
LOCKED_OUT,
CLKIN_IN,
CLK0_OUT,
CLKIN_IBUFG_OUT);
input RST_IN;
input CLKIN_IN;
output LOCKED_OUT;
output CLK0_OUT;
output CLKIN_IBUFG_OUT;
wire CLKIN_IBUFG;
wire CLKFB_IN;
wire CLK0_BUF;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
DCM DCM_INST(
.CLKIN (CLKIN_IBUFG),
.CLKFB (CLKFB_IN),
.RST (RST_IN),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSCLK (1'b0),
.DSSEN (1'b0),
.CLK0 (CLK0_BUF),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLKDV (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (),
.LOCKED (LOCKED_OUT),
.PSDONE ());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is 2
// synthesis attribute CLKFX_DIVIDE of DCM_INST is 1
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is 4
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is 30.303
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute PHASE_SHIFT of DCM_INST is 0
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synthesis translate_off
defparam DCM_INST.CLK_FEEDBACK="1X";
defparam DCM_INST.CLKDV_DIVIDE=2;
defparam DCM_INST.CLKFX_DIVIDE=1;
defparam DCM_INST.CLKFX_MULTIPLY=4;
defparam DCM_INST.CLKIN_DIVIDE_BY_2="FALSE";
defparam DCM_INST.CLKIN_PERIOD=30.303;
defparam DCM_INST.CLKOUT_PHASE_SHIFT="NONE";
defparam DCM_INST.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE="LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE="LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION="TRUE";
defparam DCM_INST.PHASE_SHIFT=0;
defparam DCM_INST.STARTUP_WAIT="FALSE";
// synthesis translate_on
IBUFG CLKIN_IBUFG_INST(
.I (CLKIN_IN),
.O (CLKIN_IBUFG));
BUFG CLK0_BUFG_INST(
.I (CLK0_BUF),
.O (CLKFB_IN));
endmodule
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В принципе в ISE есть такая приблуда Architecture Wizard - для автоматизированного встраивания DCM в проект, так вот это именно им сгенерировано.
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