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module PULT (CLK6, WRITE, ASTR, DSTR, AD, FAZA, WAIT, COD, EZ, RELE,
D_ANALOG, CLK_ANALOG, LATCH_ANALOG, D_TOK, CLK_TOK, LATCH_TOK, Q, QQ, QQQ);
input CLK6;
input WRITE; //?????? ??????/?????? LPT (0/1)
input ASTR, DSTR; //?????? ??? ???????????? ??????? ? ??????
inout [7:0] AD; //???? ??????/?????? LPT
input [23:0] FAZA;
output WAIT; wire WAIT;
output COD; wire COD; //??????????? ???????? ?????? ?? LPT (?????/???????? 1/0)
output EZ; wire EZ; //???? ?????? LPT (??????) ? ??????? ?????????
output [23:0] RELE; wire [23:0] RELE;
output [47:0] D_ANALOG; wire [47:0] D_ANALOG;
output [1:0] D_TOK; wire [1:0] D_TOK;
output CLK_ANALOG, LATCH_ANALOG; wire CLK_ANALOG, LATCH_ANALOG;
output CLK_TOK, LATCH_TOK; wire CLK_TOK, LATCH_TOK;
output Q, QQ, QQQ;
wire [15:0] CS;
wire [7:0] ADR;
wire [7:0] DATA;
wire [7:0] D_A;
wire START;
wire CLK12, CLK1K;
wire [23:0] FAZA_BUF;
wire ASTRG, DSTRG, ASTRX, DSTRX;
wire Q, QQ, QQQ;
reg [4:0] X;
wire CLK1;
//
IBUFG in1 (.I(FAZA[8]), .O(FAZA_BUF[8]));
IBUFG in2 (.I(FAZA[9]), .O(FAZA_BUF[9]));
IBUF clk1 (.I(ASTR), .O(ASTRX));
IBUF clk2 (.I(DSTR), .O(DSTRX));
BUFG clk3 (.I(ASTR), .O(ASTRG));
BUFG clk4 (.I(DSTR), .O(DSTRG));
...
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