Отправлено Grave_Digger 22 сентября 2004 г. 13:03 В ответ на: Вы сравнивали отправлено Builder 21 сентября 2004 г. 19:13

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity test_command is
port(
TCK : in std_logic; --clock 50 Mh
CLK : in std_logic; -- clock 100 Mh
TMS : in std_logic; -- control signal
TDI : in std_logic; -- data in
RST : in std_logic; --reset
TDO : out std_logic; -- data out
led1: out std_logic;
led2: out std_logic
);
end test_command;

--}} End of automatically maintained section

architecture test_command of test_command is
signal reg0:std_logic_vector (3 downto 0);
signal reg1:std_logic_vector (3 downto 0);
signal reg2:std_logic_vector (3 downto 0);
signal com:std_logic;
signal TDO_1:std_logic;
signal TDO_2:std_logic;
signal r_s : std_logic_vector(3 downto 0);

begin

TDI_reg: process (TCK, RST) -- zapolhaet shift register

begin
if RST = '1' then -- reset
r_s<=(others =>'0');
elsif rising_edge(TCK) then
if TMS = '1' then
TDO_1<=r_s(3);
r_s(3 downto 1)<=r_s(2 downto 0);
r_s(0)<=TDI;
end if;
end if;
end process TDI_reg;

reg0<= r_s when falling_edge(TMS);

Decode: process(CLK) -- Decodirovanie comandi
-- variable reg_m:std_logic_vector (3 downto 2);
begin
if rising_edge(CLK) then

reg1 <= reg0;
led1 <= '0';
led2 <= '0';
com <= '1';


C2: case reg0(3 downto 2) is

when "01" => led1 <= '1'; led2<='0';

when "10" => led1<='0'; led2 <= '1';

when "11" => led1<='1'; led2 <= '1';

when "00" => com<='0';
when others => Null;

end case C2;

end if;
end process Decode;



TDO_reg: process(TCK)
begin
if rising_edge(TMS) then
reg2<=reg1;
end if;
if rising_edge(TCK)then
if TMS = '1' then
TDO_2<= reg2(3);
reg2(3 downto 1)<=reg2(2 downto 0);
reg2(0)<='0';
end if;
end if;
end process TDO_reg;

TDO <= TDO_1 or TDO_2;
end test_command;