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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity add_sub is
port(
OP : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
C : out STD_LOGIC_VECTOR(16 downto 0)
);
end add_sub;
architecture add_sub_synt of add_sub is
signal a1 : STD_LOGIC_VECTOR(16 downto 0);
signal b1 : STD_LOGIC_VECTOR(16 downto 0);
begin
a1<='0'&A;
b1<='0'&B;
C<=a1+B1 when OP='1' else A1-B1;
end add_sub_synt;
Synplify в кристале APEX1K использовал 33 LUt и суматор умножитель построен исключительно на логике
F=130 MHz
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