Отправлено Victor® 08 декабря 2004 г. 18:07

SUBDESIGN divider
(
	clk				:INPUT;  -- Clock Input
	out[4..1]		:OUTPUT; -- Outputs
	cnt_rise[1..0]	:OUTPUT; -- For simulation
	cnt_fall[1..0]	:OUTPUT; -- For simulation
)
VARIABLE
	cnt_rise[1..0]	:DFF;    -- D type two Flip-Flop`s
	eq2_rise		:NODE;   -- Internal Node
	cnt_fall[1..0]	:DFF;	 -- D type two Flip-Flop`s
	eq2_fall		:NODE;	 -- Internal Node
BEGIN
-- Forming OUT2
	cnt_rise[].clk = clk;
	cnt_rise[].clrn = VCC;
	cnt_rise[].prn = VCC;
	
	eq2_rise = (cnt_rise[] == 2);
	
	IF eq2_rise THEN
		cnt_rise[].d = GND;
	ELSE
		cnt_rise[].d = cnt_rise[].q + 1;
	END IF;
	
	out2 = eq2_rise;
-- Forming OUT4
	cnt_fall[].clk = !clk;
	cnt_fall[].clrn = VCC;
	cnt_fall[].prn = VCC;
	
	eq2_fall = (cnt_fall[] == 2);
	
	IF eq2_fall THEN
		cnt_fall[].d = GND;
	ELSE
		cnt_fall[].d = cnt_fall[].q + 1;
	END IF;
	
	out4 = DFF(eq2_fall, !clk, , );	
	
--	Forming OUT1, OUT3
	out1 = cnt_rise0 # cnt_fall0;
	out3 = !out1;
END;