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-- One impuls Generator
-- KA
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity One_impuls is
Port (
C : in std_logic;
OE : in std_logic;
Q : out std_logic
);
end entity One_impuls;
architecture Behavioral of One_impuls is
signal Q_TMP : std_logic_vector(1 downto 0);
signal R : std_logic;
begin
process (OE,R)
begin
if R = '1' then
Q_TMP(0) <= '0';
elsif (OE'event and OE = '1') then
Q_TMP(0) <= '1';
end if;
end process;
process(C, OE)
begin
if rising_edge(C) then
Q_TMP(1) <= Q_TMP(0);
end if;
end process;
Q <= Q_TMP(1);
R <= Q_TMP(1);
end architecture Behavioral;
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