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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY gen IS
PORT
(
clock: IN STD_LOGIC;
sload: IN STD_LOGIC;
result: OUT integer RANGE 0 TO 31;
out1: OUT STD_ULOGIC;
out2: OUT STD_ULOGIC
);
END gen;
ARCHITECTURE rtl OF gen IS
SIGNAL result_reg : integer RANGE 0 TO 31;
SIGNAL tmp1: STD_ULOGIC;
SIGNAL tmp2: STD_ULOGIC;
BEGIN
p1: PROCESS (clock)
BEGIN
IF (clock'EVENT AND clock = '1') THEN
result_reg <= result_reg + 1;
END IF;
END PROCESS;
p2: PROCESS (result_reg)
BEGIN
if (result_reg>0 and result_reg<3) then tmp1<='1';
else tmp1<='0';
end if;
if (result_reg>2 and result_reg<5) then tmp2<='1';
else tmp2<='0';
end if;
END PROCESS;
result <= result_reg;
OUT1 <= tmp1;
OUT2 <= tmp2;
END rtl;
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