Отправлено AlexP 29 августа 2001 г. 17:18 В ответ на: Господа!!! А вот такой вопрос (+) отправлено Kota 29 августа 2001 г. 15:50

-- Solution 1:
-- VHDL example
-- Tested in Synplify 5.2.2a
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_example1 is
generic(data_width: integer:= 8;
address_width:integer := 8;
mem_depth: integer:= 256);
port (data: in std_logic_vector(data_width-1 downto 0);
address: in std_logic_vector(address_width-1 downto 0);
we, clk: in std_logic;
q: out std_logic_vector(data_width-1 downto 0));
end ram_example1;
architecture rtl of ram_example1 is
type mem_array is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
signal raddress : std_logic_vector(address_width-1 downto 0);
begin
l0: process (clk)
begin
if (clk = '1' and clk'event) then
raddress <= address;
if (we = '1') then
mem(CONV_INTEGER(address)) <= data;
end if;
end if;
end process;
q <= mem(CONV_INTEGER(raddress));
end rtl;

• http://www.xilinx.com/products/xaw/memory/embedded/embeddmemdoc.htm