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c:\fndtn\active\projects\clock\clock.v Error L14/C0 : #0 Error: The statements in this 'always' block are outside the scope of the synthesis policy (near symbol "end" on line 14 in file clock.v). Only an 'if' statement is allowed at the top level in this 'always' block. Please refer to the HDL Compiler reference manual for ways to infer flip-flops and latches from 'always' blocks. (VE-93)
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