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1) неоптимально
module shift1(in,out,shft);
parameter lgw=5, width=(1<<lgw)-1;
input [width:0] in;
output [width:0] out;
input [lgw-1:0] shft;
assign out={{width{in[width]}},in}>>shft;
endmodule
2) оптимально
module inv_mux_2to1 (in1,in2,out,sel);
input [31:0] in1,in2;
output [31:0] out;
input sel;
assign out=~(sel?in2:in1);
endmodule
module shift2(in,out,shft);
input [31:0] in;
output [31:0] out;
input [4:0] shft;
wire [31:0] s0,s1,s2,s3;
inv_mux_2to1 m1 (~in,{~in[31],~in[31:1]},s0,shft[0]);
inv_mux_2to1 m2 (s0,{{2{in[31]}},s0[31:2]},s1,shft[1]);
inv_mux_2to1 m3 (s1,{{4{~in[31]}},s1[31:4]},s2,shft[2]);
inv_mux_2to1 m4 (s2,{{8{in[31]}},s2[31:8]},s3,shft[3]);
inv_mux_2to1 m5 (s3,{{16{~in[31]}},s3[31:16]},out,shft[3]);
endmodule
---------------------------
для масивов
1)
module cntr1(clk, incAdr, decAdr, up, down, out, outAdr);
parameter lgw=4, lgn=3, num=1<<lgn, width=1<<lgw;
input [lgn:0] incAdr, decAdr, outAdr;
input clk,up,down;
output [width-1:0] out;
reg [width-1:0] cntr[0:num-1];
assign out=cntr[outAdr];
wire inhibit= up&down&(incAdr==decAdr);
wire inc=up&~inhibit;
wire dec=down&~inhibit;
always @(posedge clk)
begin
if (inc)
cntr[incAdr] <= cntr[incAdr]+1;
if (dec)
cntr[decAdr] <= cntr[decAdr]-1;
end
endmodule
----------------
2)
module cntr2(clk, incAdr, decAdr, up, down, out, outAdr);
parameter lgw=4, lgn=3, num=1<<lgn, width=1<<lgw;
input [lgn:0] incAdr, decAdr, outAdr;
input clk,up,down;
output [width-1:0] out;
reg [width-1:0] cntr[0:num-1];
integer i;
wire [num-1:0] inc=up<<incAdr;
wire [num-1:0] dec=down<<decAdr;
wire [width-1:0] add=cntr[incAdr]+1;
wire [width-1:0] sub=cntr[decAdr]-1;
assign out=cntr[outAdr];
always @(posedge clk)
begin
for(i=0;i<num;i=i+1)
cntr[i]= inc[i]^dec[i] ? (inc[i] ? add : sub):cntr[i];
end
endmodule
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