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3.8 regs
Assignments to a reg are made by procedural assignments (see 6.2 and 9.2). Since the reg holds a value
between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level
sensitive (i.e., RS and transparent latches) storage elements can be modeled. A reg needs not represent a
hardware storage element since it can also be used to represent combinatorial logic.
Ну вобщем в Verilog такое извращение
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