[an error occurred while processing this directive]
|
module divider4
( input clk, rst,
output reg div4 );
reg [1:0] div = 2'b00 ;
always @(posedge clk) div4 <= div[1] ;
always @(negedge clk, posedge rst) if (rst) div <= 2'b00 ; else div <= div + 1 ;
endmodule
E-mail: info@telesys.ru