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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux8_1 is
port(
sel : in STD_LOGIC_vector(2 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0 );
q : out STD_LOGIC
);
end mux8_1;
architecture mux8_1 of mux8_1 is
begin
with sel select
q<=d(0)when "000",
d(1)when "001",
d(2)when "010",
d(3)when "011",
d(4)when "100",
d(5)when "101",
d(6)when "110",
d(7)when others;
end mux8_1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux4_1 is
port(
sel : in STD_LOGIC_vector(1 downto 0);
d : in STD_LOGIC_VECTOR(3 downto 0 );
q : out STD_LOGIC
);
end mux4_1;
architecture mux4_1 of mux4_1 is
begin
with sel select
q<=d(0)when "00",
d(1)when "01",
d(2)when "10",
d(3)when others;
end mux4_1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux32_1 is
port(
sel : in STD_LOGIC_vector(4 downto 0);
d : in STD_LOGIC_VECTOR(31 downto 0 );
q : out STD_LOGIC
);
end mux32_1;
architecture mux32_1 of mux32_1 is
component mux8_1 is
port(
sel : in STD_LOGIC_vector(2 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0 );
q : out STD_LOGIC
);
end component;
component mux4_1 is
port(
sel : in STD_LOGIC_vector(1 downto 0);
d : in STD_LOGIC_VECTOR(3 downto 0 );
q : out STD_LOGIC
);
end component;
signal x0,x1,x2,x3:std_logic;
signal x4:std_logic_vector(3 downto 0);
begin
m0:mux8_1 port map(
sel=>sel(2 downto 0),
d=>d(7 downto 0),
q=>x0
);
m1:mux8_1 port map(
sel=>sel(2 downto 0),
d=>d(15 downto 8),
q=>x1
);
m2:mux8_1 port map(
sel=>sel(2 downto 0),
d=>d(23 downto 16),
q=>x2
);
m3:mux8_1 port map(
sel=>sel(2 downto 0),
d=>d(31 downto 24),
q=>x3
);
x4<=x3&x2&x1&x0;
m4:mux4_1 port map(
sel=>sel(4 downto 3),
d=>x4,
q=>q
);
end mux32_1;
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