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// MAX+plus II Verilog Example
// Combinatorial Always Statement
// Copyright (c) 1994 Altera Corporation
module proc (d, q);
input [5:0] d;
output [2:0] q;
integer num_bits;
always @(d)
begin: block
integer i;
num_bits = 0;
for (i = 0; i < 6; i = i + 1)
if (d[i] == 1)
num_bits = num_bits + 1;
end
assign q = num_bits;
endmodule
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