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1)
library ieee;
use ieee.std_logic_1164.all;
entity test is
generic ( n : integer := 5 -- разрядность
);
port (
din : in std_logic_vector(n-1 downto 0);
dout : out std_logic_vector(n-1 downto 0)
);
end test;
architecture core of test is
begin
in_out : process
begin
for i in 0 to (n-1) loop
dout((n-1)-i) <= din(i);
end loop;
end process in_out;
end core;
2)
library ieee;
use ieee.std_logic_1164.all;
entity parity is
port ( ad : in std_logic_vector(31 downto 0);
cben : in std_logic_vector(3 downto 0);
parity : out std_logic
);
end parity;
architecture core of parity is
signal ad_cben : std_logic_vector(35 downto 0);
begin
parity_check : process
variable parity_bit : std_logic;
begin
ad_cben <= ad & cben;
parity_bit := '0';
for i in 0 to 35 loop
parity_bit := parity_bit xor ad_cben(i);
end loop;
parity <= parity_bit;
end process parity_check;
end core;
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