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odule fpdiv(DIVz, A, B, Q);
input [3:0] A;
input [3:0] B;
output [3:0] Q;
output DIVz;
//}} End of automatically maintained section
wire [7:0] REMAINDERS0;
wire [7:0] REMAINDERS1;
wire [7:0] REMAINDERS2;
wire [7:0] REMAINDERS3;
wire [7:0] REMAINDERS4;
wire [7:0] DIVISORS0;
wire [7:0] DIVISORS1;
wire [7:0] DIVISORS2;
wire [7:0] DIVISORS3;
wire [7:0] DIVISORS4;
wire [3:0] Q_TEMP;
wire ZERO;
supply0 [3:0] Z0;
supply0 [3:0] Z1;
assign DIVISORS0 = {Z0, B};
assign DIVISORS1 = {DIVISORS0[6:0], 1'b0};
assign DIVISORS2 = {DIVISORS1[6:0], 1'b0};
assign DIVISORS3 = {DIVISORS2[6:0], 1'b0};
assign DIVISORS4 = {DIVISORS3[6:0], 1'b0};
assign REMAINDERS4 = {Z1, A};
assign REMAINDERS3 = (Q_TEMP[3] === 1'b1) ? (REMAINDERS4-DIVISORS3) : REMAINDERS4;
assign REMAINDERS2 = (Q_TEMP[2] === 1'b1) ? (REMAINDERS3-DIVISORS2) : REMAINDERS3;
assign REMAINDERS1 = (Q_TEMP[1] === 1'b1) ? (REMAINDERS2-DIVISORS1) : REMAINDERS2;
assign REMAINDERS0 = (Q_TEMP[0] === 1'b1) ? (REMAINDERS1-DIVISORS0) : REMAINDERS1;
assign Q_TEMP[0] = (REMAINDERS1 endmodule
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assign DIVz = (ZERO === 1'b1) ? 1'b1 : 1'b0;
assign Q = (ZERO === 1'b1) ? {4{1'b0}} : Q_TEMP;
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