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|
module hdl7(CLK, F, LED1);
input CLK;
output reg F;
output reg LED1;
wire [1:0] out2; // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
foo FOO(.out1(out2));
always @(posedge CLK)
begin
F <= out2[0];
LED1 <= out2[1];
end
endmodule
module foo(out1)
output wire [1:0] out1;
assign out1 = {1,1};
endmodule
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