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Ведется подсчет импульсов tclk и каждый 32 импульс генерится trfs длительностью tclk. Вобщем, получается делитель на 32.
Я в VHDL начинающий, хотелось бы узнать Ваше мнение по поводу реализации этой задачи.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity tdm2 is
port (
reset: in std_logic;
tclk_ext: in std_logic;
trfs: out std_logic
);
end tdm2;
architecture Behavioral of tdm2 is
component BUFG
port (I : in std_logic; O : out std_logic);
end component;
type state_type is (counting, term);
signal tclk : std_logic;
signal state : state_type;
signal count_strobe : std_logic;
signal end_word : std_logic;
signal count : integer range 0 to 31;
constant TERMINAL_COUNT : integer range 0 to 31 := 31;
begin
tclk_buf: BUFG port map (I=>tclk_ext, O=>tclk);
trfs <= end_word;
count_tclk_proc:process(tclk, reset, state)
begin
if reset = '1' then
state <= counting;
elsif falling_edge(tclk) then
case state is
when counting =>
count <= count + 1;
if count = TERMINAL_COUNT - 1 then
count_strobe <= '1';
elsif count = TERMINAL_COUNT then
count <= 0;
state <= term;
count_strobe <= '0';
end if;
when term =>
count <= 0;
count <= count + 1;
state <= counting;
end case;
end if;
end_word <= count_strobe and tclk;
end process;
end Behavioral;
Тест бенч
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tdm2_tdm2_tb_vhd_tb IS
END tdm2_tdm2_tb_vhd_tb;
ARCHITECTURE behavior OF tdm2_tdm2_tb_vhd_tb IS
COMPONENT tdm2
PORT(
reset : IN std_logic;
tclk_ext : IN std_logic;
trfs : OUT std_logic
);
END COMPONENT;
SIGNAL reset : std_logic;
SIGNAL tclk_ext : std_logic;
SIGNAL trfs : std_logic;
BEGIN
uut: tdm2 PORT MAP(
reset => reset,
tclk_ext => tclk_ext,
trfs => trfs
);
-- Reset Process --------------------------------------------------------------
RESET_PROC: process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
-- CLK-GENERATOR ----------------------------------------------------
CLK_GENERATOR: process
begin
tclk_ext <= '1';
wait for 50 ns;
tclk_ext <= '0';
wait for 50 ns;
end process;
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
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