[an error occurred while processing this directive]
|
always @ (posedge wrH or posedge wrL or posedge clk)
begin
if(wrH || wrL)
begin
flag <= 1;
end
else
begin
if(tmp) flag <= 0;
end
end
always @(posedge clk)
if(~flag)tmp<=0; else tmp <= 1;
Тут аснхронные основному клоку сигналы только wrH wrL
always @(posedge armClk)
if(wrH) newData[15:8] <= in;
итд.
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