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это исходник
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package DISPLAY is
type LED_DISPLAY is record
SEG_A : std_logic;
SEG_B : std_logic;
SEG_C : std_logic;
SEG_D : std_logic;
SEG_E : std_logic;
SEG_F : std_logic;
SEG_G : std_logic;
SEG_DOT : std_logic;
end record;
-- Declare constants
constant SYM_0 :std_logic_vector(6 downto 0):="1000000";
constant SYM_1 :std_logic_vector(6 downto 0):="1111001";
constant SYM_2 :std_logic_vector(6 downto 0):="0100100";
constant SYM_3 :std_logic_vector(6 downto 0):="0110000";
constant SYM_4 :std_logic_vector(6 downto 0):="0011001";
constant SYM_5 :std_logic_vector(6 downto 0):="0010010";
constant SYM_6 :std_logic_vector(6 downto 0):="0000010";
constant SYM_7 :std_logic_vector(6 downto 0):="1111000";
constant SYM_8 :std_logic_vector(6 downto 0):="0000000";
constant SYM_9 :std_logic_vector(6 downto 0):="0010000";
constant SYM_A :std_logic_vector(6 downto 0):="0001000";
constant SYM_B :std_logic_vector(6 downto 0):="0000011";
constant SYM_C :std_logic_vector(6 downto 0):="1000110";
constant SYM_D :std_logic_vector(6 downto 0):="0100001";
constant SYM_E :std_logic_vector(6 downto 0):="0000110";
constant SYM_F :std_logic_vector(6 downto 0):="0001110";
-- Declare functions and procedure
procedure hex_to_seg ( variable HEX_q : in std_logic_vector(3 downto 0);
signal SEGMETS : out std_logic_vector(6 downto 0) );
procedure VECTOR_to_RECORD (variable VECTOR : in std_logic_vector(6 downto 0);
signal REC : out LED_DISPLAY );
end DISPLAY;
package body DISPLAY is
procedure hex_to_seg ( variable HEX_q : in std_logic_vector(3 downto 0);
signal SEGMETS : out std_logic_vector(6 downto 0) ) is
begin
with HEX_q select
SEGMETS <= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
end procedure ;
procedure VECTOR_to_RECORD (variable VECTOR : in std_logic_vector(6 downto 0);
signal REC : out LED_DISPLAY ) is
begin
REC.SEG_A <= VECTOR(0);
REC.SEG_B <= VECTOR(1);
REC.SEG_C <= VECTOR(2);
REC.SEG_D <= VECTOR(3);
REC.SEG_E <= VECTOR(4);
REC.SEG_F <= VECTOR(5);
REC.SEG_G <= VECTOR(6);
REC.SEG_DOT<='1';
end procedure;
end DISPLAY;
это лог ошибок
Started process "Check Syntax".
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=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "E:/work/wip/my_type.vhd" in Library work.
Package
ERROR:HDLParsers:164 - "E:/work/wip/my_type.vhd" Line 59. parse error, unexpected WITH
ERROR: XST failed
Process "Check Syntax" did not complete.
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