|
|
module rg_xor (clk, in, clr, ce, out);
parameter znachenie = 8'd2;
parameter width = 8;
input clk;
input [width-1:0] in;
input clr;
input ce;
output [width-1:0] out;
reg [width-1:0] fdce_dffe;
assign out = fdce_dffe ^ znachenie;
always @ (posedge clk or posedge clr)
begin
if (clr == 1'b1)
fdce_dffe <= 8'h00;
else if (ce == 1'b1)
fdce_dffe <= in ^ znachenie;
end
endmodule
E-mail: 
info@telesys.ru
