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/pre
module IO_SPI(SSEL,SCK,MOSI,MISO,in_port,out_port,GlobalClr);
input SSEL,SCK,MOSI,GlobalClr;
output MISO;
input [23:0]in_port;
output[23:0]out_port;
//////////////////////////////////////////
reg[23:0]out_port;
reg[4:0]bit_cntr;
reg[23:0]byte;
reg tmp;
//////////////////////////////////////////
assign MISO = SSEL ? 1'bz : tmp;
//////////////////////////////////////////
always@(posedge SCK)
begin
if(SSEL)
begin
bit_cntr = 5'b00000;
end
else
begin
byte[bit_cntr] = MOSI;
tmp = in_port[bit_cntr];
bit_cntr = bit_cntr + 5'b00001;
end
end
always@(negedge SCK)
begin
if(GlobalClr)
begin
if(bit_cntr == 24) out_port = byte;
end
else
begin
out_port = 24'hffffff;
end
end
endmodule
/pre
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