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process(clk,rst)
begin
if rst = '1' then
cnt_wr <= shift;
cnt_rd <= (others => '0');
elsif clk = '1' and clk'event then
if we = '1' then
cnt_wr <= cnt_wr + 1;
cnt_rd <= cnt_rd + 1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(we = '1') then
ram_sh(conv_integer(cnt_wr)) <= data_IN;
end if;
addr_rd <= cnt_rd;
end if;
end process;
DATA_out <= ram_sh(conv_integer(addr_rd));
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