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Cadence IUS 5.6
ISR200512191407_IUS56
Cadence IC Design 5251
http://www.cadence.com
Products included in Release- ICOA5251
Product # Product Name Version
111 Cadence(R) Design Framework II 5.2
12141 Cadence(R) Design Framework Integrator's Toolkit 5.2
206 Virtuoso(R) Simulation Environment 5.2
207 Waveform 5.2
21060 Virtuoso(R) Schematic VHDL Interface 5.2
21400 Virtuoso(R) Schematic Editor Verilog(R) Interface 5.2
276 Virtuoso(R) Schematic Editor HSPICE Interface 5.2
283 Open Simulation System 5.2
300 Virtuoso(R) Layout Editor 5.2
3000 Virtuoso(R)-XL Layout Editor 5.2
3011 Virtuoso XL Basic 5.1.41
302 Virtuoso(R) Schematic Layout Option 5.2
305 Virtuoso(R) Compactor 5.2
3100 Virtuoso(R) Custom Placer 11.3
311 Virtuoso(R) Layout Editor Turbo 5.2
3111 Virtuoso LE Turbo Basic 5.1.41
3200 Virtuoso(R) Custom Router 11.3
32100 Virtuoso(R) Analog Oasis Run-Time Option 5.2
32101 Cadence(R) OASIS for RFDE 5.2
32120 Virtuoso(R) Electronic Design for Manufacturability Option 5.2
32125 Cadence(R) Analog Corners Analysis Option 5.2
32130 Cadence(R) Analog Circuit Optimizer Option 5.2
32140 Cadence(R) Analog Mixed-Signal Simulation Interface Option 5.2
32150 Cadence(R) SPICE 5.2
32760 Virtuoso(R) Analog HSPICE Interface Option 5.2
3300 Virtuoso(R) Chip Assembly Router 11.3
33301 Cadence(R) Analog Mixed-Signal Back-Annotation Interface Option 5.2
34500 Virtuoso(R) Schematic Editor 5.2
34510 Virtuoso(R) Analog Design Environment 5.2
34511 Spectre(R)-RF Substrate Coupling Analysis Option 5.2
34530 Cadence(R) Analog Distributed Processing Option 5.2
34570 Virtuoso(R) Analog VoltageStorm Option 4.1
34580 Virtuoso(R) Analog ElectronStorm Option 4.1
365 Dracula(R) Graphical User Interface 5.2
4000 Virtuoso(R) Chip Editor 5.2
5100 Virtuoso(R) Layout Migrate 5.2
570 Virtuoso(R) Schematic Composer to design compiler integration 5.2
681 Cadence(R) RC Network Reducer Option 3.0
70000 Virtuoso(R) AMS Designer Environment 1.0
70110 Dracula(R) Design Rule Checker 4.8
70120 Dracula(R) Layout Vs. Schematic Verifier 4.8
70130 Dracula(R) Parasitic Extractor 4.8
70510 Dracula(R) Physical Verification Suite 4.8
70520 Dracula(R) Physical Verification and Extraction Suite 4.8
71110 Diva(R) Design Rule Checker 4.4.5
71120 Diva(R) Layout Vs. Schematic Verifier 4.4.5
71130 Diva(R) Parasitic Extractor 4.4.5
71510 Diva(R) Physical Verification Suite 4.4.5
71520 Diva(R) Physical Verification and Extraction Suite 4.4.5
900 Cadence(R) SKILL Development Environment 5.2
940 Virtuoso(R) EDIF 200 Reader 5.2
945 Virtuoso(R) EDIF 200 Writer 5.2
972 SDLIN 5.2
974 CDLIN 5.2
TW01 Cadence(R) team design manager 4.2
TW02 Cadence(R) team design project adminsitrator 4.2
Cadence MMSIM 60
Ultrasim 4.1 this is only one simulator - FastSPICE.
MMSIM 6.0 - this is 4 simulators: SPICE, FastSPICE, SPECTRE (!), SPECTRE RF (!).
Thus, Ultrasim don't contain SPECTRE, SPECTRE RF and SPICE simulators.
Virtuoso Multi-mode Simulation delivers the SPICE, FastSPICE, RF, and analog mixed-signal capabilities to simulate any analog, mixed-signal, or RF design.
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E-mail: 
info@telesys.ru
