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Как описать стандартную макрофункцию lpm_ram_dq (Квартус или МАХ+) на Veriloge???
Вот VHDL:
COMPONENT lpm_ram_dq
GENERIC (LPM_WIDTH : POSITIVE;
LPM_WIDTHAD : POSITIVE;
LPM_NUMWORDS : NATURAL := 0;
LPM_INDATA : STRING := "REGISTERED";
LPM_ADDRESS_CONTROL : STRING := "REGISTERED";
LPM_OUTDATA : STRING := "REGISTERED";
LPM_FILE : STRING := "UNUSED";
LPM_TYPE : STRING := "LPM_RAM_DQ";
LPM_HINT : STRING := "UNUSED" );
PORT (data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
address : IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
inclock, outclock : IN STD_LOGIC := '0';
we : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) );
END COMPONENT;
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