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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity en_counter is
port (a : in std_logic_vector (7 downto 0);
b : in std_logic_vector (7 downto 0);
s : out std_logic_vector (8 downto 0)
);
end en_counter;
architecture sum_behave of en_counter is
begin
s <= ('0' & a) + ('0' & b) ;
end sum_behave;
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