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/* always block with combinational logic*/
always @(state or enable or data_in) begin
/* Default values for FSM outputs*/
state0 <= 1'b0;
state1 <= 1'b0;
state2 <= 1'b0;
data_out <= 1'b0;
case (state)
idle : if (enable) begin
state0 <= 1'b1;
data_out <= data_in[0];
next_state <= read;
end
else begin
next_state <= idle;
end
read : if (enable) begin
state1 <= 1'b1;
data_out <= data_in[1];
next_state <= write;
end
else begin
next_state <= read;
end
write : if (enable) begin
state2 <= 1'b1;
data_out <= data_in[2];
next_state <= idle;
end
else begin
next_state <= write;
end
/* Default assignment for simulation */
default : next_state <= deflt;
endcase
end
endmodule
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