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Был тут как то такой текст:
library ieee;
use ieee.STD_logic_1164.ALL;
entity counter is
port(clk : in std_logic;
rst : in std_logic;
dfr : out std_logic_vector(17 downto 0);
ref : out std_logic
);
end counter;
architecture count_rtl of counter is
SIGNAL div : Std_logic_vector(17 downto 0);
SIGNAL car : Std_logic_vector(13 downto 0);
begin
divider: process(clk,rst)
begin
if rst='0' then
div <= "000000000000000000";
car <= "00000000000000";
elsif(clk'event and clk='1') then
div(0) <= not div(0);
div(1) <= div(0) xor div(1);
div(2) <= ((not div(0) and div(1) and div(2)) or (div(0) and div(1) and (not div(2))) or (not div(1) and div(2)));
car(0) <= not div(0) and div(1) and div(2);
div(3) <= (not div(3) and car(0)) or (not car(0) and div(3));
car(1) <= not div(0) and div(1) and div(2) and div(3);
div(4) <= (not div(4) and car(1)) or (not car(1) and div(4));
div(5) <= (not div(5) and div(4) and car(1)) or (not(div(4) and car(1)) and div(5));
car(2) <= div(4) and div(5);
div(6) <= (not div(6) and car(2) and car(1)) or (not(car(2) and car(1)) and div(6));
car(3) <= div(6) and car(2);
div(7) <= (not div(7) and car(3) and car(1)) or (not(car(3) and car(1)) and div(7));
car(4) <= div(0) and (not div(1)) and div(2) and div(3);
car(5) <= div(4) and div(5) and div(6) and div(7);
car(6) <= car(4) and car(5);
div(8) <= (not div(8) and car(6)) or (not car(6) and div(8));
div(9) <= ((div(8) xor div(9)) and car(6)) or (not car(6) and div(9));
car(7) <= car(4) and car(5) and div(8) and div(9);
div(10) <= (not div(10) and car(7)) or (not car(7) and div(10));
div(11) <= ((div(10) xor div(11)) and car(7)) or (not car(7) and div(11));
car(8) <= div(8) and div(9) and div(10) and div(11);
car(9) <= car(4) and car(5) and car(8);
div(12) <= (not div(12) and car(9)) or (not car(9) and div(12));
div(13) <= ((div(12) xor div(13)) and car(9)) or (not car(9) and div(13));
car(10) <= div(12) and div(13);
car(11) <= car(4) and car(5) and car(8) and car(10);
div(14) <= (not div(14) and car(11)) or (not car(11) and div(14));
div(15) <= ((div(14) xor div(15)) and car(11)) or (not car(11) and div(15));
car(12) <= div(12) and div(13) and div(14) and div(15);
car(13) <= car(4) and car(5) and car(8) and car(12);
div(16) <= (not div(16) and car(13)) or (not car(13) and div(16));
div(17) <= ((div(16) xor div(17)) and car(13)) or (not car(13) and div(17));
end if;
end process divider;
dfr <= div;
ref <= div(6);
end count_rtl;
Где car - это конвейризированный перенос.
Вот так я извращался, начиная знакомиться с VHDL.
А как написать в таком же стиле обратный счетчик?
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