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|
assign q= q_pos ^ q_neg;
module ddrff
(
input clk,
input clr,
input d,
output q
);
reg q_pos, q_neg;
always @(posedge clk)
if (clr) q_pos <= q_neg ^ ~clr;
else q_pos <= q_neg ^ d;
always @(negedge clk)
if (clr) q_neg <= q_pos ^ ~clr;
else q_neg <= q_pos ^ d;
endmodule
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