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// CIC-фильтр дециматор
module cic_dec (
clk,
fs1,
fs2,
d,
q
);
//parameter N = 1;
//parameter M = 1;
//parameter R = 128;
input clk;
input fs1;
input fs2;
input [15:0] d;
output [15:0] q;
reg fs1_reg;
reg fs2_reg;
wire add;
wire sub;
wire [23:0] int_out;
wire clken1,clken2;
wire areset;
assign add = 1'b1;
assign sub = 1'b0;
assign areset = 1'b0;
//===================================================
//Синхронизатор
always @(posedge clk)
fs1_reg <= fs1;
always @(posedge clk)
fs2_reg <= fs2;
assign clken1 = fs1 & ~fs1_reg;
assign clken2 = fs2 & ~fs2_reg;
//===================================================
//Integrator-1
wire [23:0] in_int1,out_int1;
assign in_int1 = { d[15], d[15], d[15], d[15], d[15], d[15], d[15], d[15], d[15:0] };
altaccumulate1 altaccum_int1(
.aclr(areset),
.add_sub(add),
.clken(clken1),
.clock(clk),
.data(in_int1),
.result(out_int1));
assign int_out = out_int1;
//===================================================
//Comb-1
reg [23:0] comb_z1;
wire [23:0] dataa1,datab1,res_comb1;
assign datab1 = int_out;
assign dataa1 = comb_z1;
lpm_add_sub5 lpm_add_sub5_comb1(
.add_sub(sub),
.clken(clken2),
.clock(clk),
.dataa(dataa1),
.datab(datab1),
.result(res_comb1));
always @(posedge clk)
if (clken2) begin
comb_z1 <= datab1;
end
assign q[15:0] = res_comb1[15:0];
endmodule
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