[an error occurred while processing this directive]
reg [1:0] cntr;always @(posedge clock) if (cntr_a[1]) cntr <= 2'b00; else cntr <= cntr + 1'b1;reg half_dly;always @(negedge clock) half_dly <= cntr[1];assign out = cntr_a[1] | half_dly;
reg half_dly;always @(negedge clock) half_dly <= cntr[1];
assign out = cntr_a[1] | half_dly;