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module sr (CLK, RST, TO_RG, AUDIO_LOAD, MEMORY, DATA);
input CLK, RST, AUDIO_LOAD;
input [5:0] TO_RG;
output DATA; reg DATA;
output [5:0] MEMORY; reg [5:0] MEMORY;
always @ (posedge iCLK or posedge iRST)
begin
if (RST) begin
DATA<=1'b0;
MEMORY<=6'b0;
end
else if (AUDIO_LOAD) begin
MEMORY <= TO_RG;
end
else begin
MEMORY <= (MEMORY << 1);
DATA = MEMORY[5];
end
end
endmodule