[an error occurred while processing this directive]
|
module test(reset,clk,a,b,c)
input reset,clk;
input [7:0] a,b;
output reg [7:0] c;reg [2:0] i;
always @(posedge clock or posedge reset)
if (reset) begin
i <= 3'h0;
c <= 8'h00;
end else begin
i <= i + 1'b1;
if (i == 3'h0)
if (a == b) c <= a;
else if (a > b) c <= b;
end
endmodule
Причем вот это
if (a == b) c <= a;
else if (a > b) c <= b;
if (a >= b) c <= b;