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Вот текстовичёк к таймеру
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity del_clk is
Port ( set : in STD_LOGIC;
out_clk : out STD_LOGIC;
clk : in STD_LOGIC;
prog : in STD_LOGIC_VECTOR (15 downto 0));
end del_clk;
architecture Behavioral of del_clk is
signal st : STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";
signal outsig : STD_LOGIC:='0';
signal setup : STD_LOGIC:='0';
begin
process(set,outsig)
variable crt : integer:=0;
begin
if set='1' then
crt := crt + 1;
end if;
if outsig = '0' then
crt := crt - 1;
end if;
if crt=0 then
setup<='0';
else
setup<='1';
end if;
end process;
process(clk)
begin
if (clk='1' and setup='1') then
if st=prog then
st<= conv_std_logic_vector(0,16);
else st<=st+1;
end if;
end if;
if st=prog then
out_clk <= '1';
outsig <= '1';
else
out_clk <= '0';
outsig <= '0';
end if;
end process;
end Behavioral;
--------------------------------------------------------------------
При моделировании при prog=3 выдаёт следующее
_ _ _ _ _ _ _ _ _ _ _
_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ clk
___ ___ ___ ___ ___ ___
_| |___| |___| |___| |___| |___| | set
________________________________________
_____| setup
___ ___
___________________| |___________| |______ out_clk
Где @ зарыта?
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