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В блоках Б и В подключаешь блок А как component.
Аналогично в блоке Д - два компонента : Б и В.
Пример - в дизайне самого верхнего уровня три компонента (каждый из них тоже может содержать компоненты более низкого уровня) :
*******************************************************************
library ieee;
use ieee.STD_logic_1164.ALL;
use work.my_types.all;
entity design is
port(clock : in std_logic;
reset : in std_logic;
c_in : in std_logic;
c_out : out std_logic;
div_clk : out std_logic_vector(17 downto 0);
des_led : out std_logic_vector(7 downto 0);
back : out std_logic;
des_data : out char
);
end design;
architecture design_rtl of design is
component counter
port(clk : in std_logic;
rst : in std_logic;
dfr : out std_logic_vector(17 downto 0);
ref : out std_logic
);
end component;
-- for all : counter use entity work.counter;
component shifter
port(clk : in std_logic;
rst : in std_logic;
carrier : out std_logic;
line : out std_logic;
led : out std_logic_vector(7 downto 0)
);
end component;
--for all : shifter use entity work.shifter;
component decoder
port(clk : in std_logic;
rst : in std_logic;
carrier : in std_logic;
data : out char
);
end component;
--for all : decoder use entity work.decoder;
signal int_dclk : std_logic;
signal int_cr : std_logic;
signal int_dir : std_logic;
signal int_dfr : std_logic_vector(17 downto 0);
signal int_led : std_logic_vector(7 downto 0);
signal int_dat : char;
begin
cnt: counter
port map(clk => clock,
rst => reset,
dfr => int_dfr,
ref => int_dclk
);
div_clk <= int_dfr;
c_out <= int_dclk;
sht: shifter
port map(clk => c_in,
rst => reset,
carrier => int_cr,
line => int_dir,
led => int_led
);
des_led <= int_led;
back <= int_cr;
dec: decoder
port map(clk => int_dir,
rst => reset,
carrier => int_cr,
data => int_dat
);
des_data <= int_dat;
end design_rtl;
*****************************************************************
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