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В ModelSim нужно описывать входное воздействие на языке, и затем объединять его с самим проектом в тестбенче.
Пример для VHDL, который я здесь приводил уже не раз (для Verilog - метода та же) :
******** Модуль проекта (проект с иерархией) ************************
library ieee;
use ieee.STD_logic_1164.ALL;
use work.my_types.all;
entity design is
port(clock : in std_logic;
reset : in std_logic;
c_in : in std_logic;
c_out : out std_logic;
div_clk : out std_logic_vector(17 downto 0);
des_led : out std_logic_vector(7 downto 0);
back : out std_logic;
des_data : out char
);
end design;
architecture design_rtl of design is
component counter
port(clk : in std_logic;
rst : in std_logic;
dfr : out std_logic_vector(17 downto 0);
ref : out std_logic
);
end component;
for all : counter use entity work.counter;
component shifter
port(clk : in std_logic;
rst : in std_logic;
carrier : out std_logic;
line : out std_logic;
led : out std_logic_vector(7 downto 0)
);
end component;
for all : shifter use entity work.shifter;
component decoder
port(clk : in std_logic;
rst : in std_logic;
carrier : in std_logic;
data : out char
);
end component;
for all : decoder use entity work.decoder;
signal int_dclk : std_logic;
signal int_cr : std_logic;
signal int_dir : std_logic;
signal int_dfr : std_logic_vector(17 downto 0);
signal int_led : std_logic_vector(7 downto 0);
signal int_dat : char;
begin
cnt: counter
port map(clk => clock,
rst => reset,
dfr => int_dfr,
ref => int_dclk
);
div_clk <= int_dfr;
c_out <= int_dclk;
sht: shifter
port map(clk => c_in,
rst => reset,
carrier => int_cr,
line => int_dir,
led => int_led
);
des_led <= int_led;
back <= int_cr;
dec: decoder
port map(clk => int_dir,
rst => reset,
carrier => int_cr,
data => int_dat
);
des_data <= int_dat;
end design_rtl;
************** Описание входного воздействия для этого проекта ******
library ieee;
use ieee.STD_logic_1164.ALL;
entity clk_emul is
port(e_clk1 : out std_logic;
e_clk2 : out std_logic;
e_reset : out std_logic
);
end clk_emul;
architecture clk_signal of clk_emul is
begin
cm1: process -- Тактовый сигнал номер раз :)
begin
wait for 25 ns;
e_clk1 <= '0';
wait for 25 ns;
e_clk1 <= '1';
end process cm1;
cm2: process -- Тактовый сигнал номер два :)
begin
wait for 3200 ns;
e_clk2 <= '0';
wait for 3200 ns;
e_clk2 <= '1';
end process cm2;
rm: process -- Сигнал сброса
begin
e_reset <= '0';
wait for 120 us;
e_reset <= '1';
wait;
end process rm;
end clk_signal;
*************** Тестбенч ********************************************
library ieee;
use ieee.STD_logic_1164.ALL;
use work.my_types.all;
entity des_test is
end des_test;
architecture test_box of des_test is
component clk_emul
port(e_clk1 : out std_logic := 'Z';
e_clk2 : out std_logic := 'Z';
e_reset : out std_logic := 'Z'
);
end component;
for all : clk_emul use entity work.clk_emul;
component design
port(clock : in std_logic;
reset : in std_logic;
c_in : in std_logic;
c_out : out std_logic;
div_clk : out std_logic_vector(17 downto 0);
des_led : out std_logic_vector(7 downto 0);
des_data : out char
);
end component;
for all : design use entity work.design;
signal clock : std_logic;
signal lf_clk : std_logic;
signal reset : std_logic;
signal olf_clk : std_logic;
signal dc : std_logic_vector(17 downto 0);
signal dl : std_logic_vector(7 downto 0);
signal dd : char;
begin
ce: clk_emul
port map(e_clk1 => clock,
e_clk2 => lf_clk,
e_reset => reset
);
des: design
port map(clock => clock,
reset => reset,
c_in => lf_clk,
c_out => olf_clk,
div_clk => dc,
des_led => dl,
des_data => dd
);
end test_box;
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