library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mng_pch is
port (
-- Ñáðîñ è òàêòèðîâàíèå
RESET : in std_logic;
-- Øèíà SPI
MISO : out std_logic;
MOSI : in std_logic;
CE, SPI_CLK : in std_logic;
-- Àòòåíþàòîð Â× ¹1
AT1 : out std_logic_vector (4 downto 0);
AT1_LE : out std_logic;
-- Àòòåíþàòîð Ï× ¹2, 3, 4, 5
AT2_DT, AT2_CLK, AT2_LE : out std_logic;
AT3_DT, AT3_CLK, AT3_LE : out std_logic;
AT4_DT, AT4_CLK, AT4_LE : out std_logic;
AT5_LE : out std_logic;
-- Ôàçîâûé ðåçèñòîð
R1_SD, R1_CLK, R1_CS : out std_logic;
-- Ðåçèñòîð ïîäñòðîè÷íûé Ã1
DAC1_DT, DAC1_CLK, DAC1_CS : out std_logic;
-- PLL 1, 2, 3, 4
PLL_LE, PLL_DT, PLL_CLK : out std_logic_vector (3 downto 0);
PLL_LD : in std_logic_vector (3 downto 0);
-- Ïåðåêëþ÷àòåëè
SW_A, SW_B : out std_logic;
-- DDS
DDS1_RST, DDS1_CS, DDS1_CLK, DDS1_DTIN : out std_logic;
DDS1_DTOUT : in std_logic

-- Îòëàäêà
-- int_clk_tmp : out std_logic
-- DT_PLL_tmp : out std_logic_vector (23 downto 0)
-- dt_spi_tmp : out std_logic_vector (7 downto 0)

);
end mng_pch;

architecture Arch_mng_pch of mng_pch is
-- Îñöèëÿòîð
--component oscill
-- PORT (
-- oscena : IN STD_LOGIC ;
-- osc : OUT STD_LOGIC
-- );
--end component;

signal INT_CLK : std_logic;

-- Øèíà SPI
signal READY_DT_SPI : std_logic;
signal DT_SPI : std_logic_vector (7 downto 0);

-- Àòòåíþàòîðû
type tDT_AT is array (0 to 4) of std_logic_vector (4 downto 0);
type tflgAT is array (0 to 4) of boolean;
type tcntAT is array (0 to 4) of integer range 0 to 12;

signal DT_AT : tDT_AT;
signal fNewAT, fWrAT, fReadyAT : tflgAT;
signal cntAT : tcntAT;
-- Ôàçîâûé ðåçèñòîð
signal DT_PhRes : std_logic_vector (7 downto 0);
signal fNewPhRes, fWrPhRes, fReadyPhRes : boolean;
signal cntPhRes : integer range 0 to 11;
-- Ðåçèñòîð Ã1
signal DT_ResG1 : std_logic_vector (7 downto 0);
signal fNewResG1, fWrResG1, fReadyResG1 : boolean;
signal cntResG1 : integer range 0 to 11;
-- PLL
type tDT_PLL is array (0 to 3) of std_logic_vector (23 downto 0);
type tflgPLL is array (0 to 3) of boolean;
type tcntPLL is array (0 to 3) of integer range 0 to 27;

signal DT_PLL : tDT_PLL;
signal fNewPLL, fReadyPLL, fWrPLL : tflgPLL;
signal cntPLL : tcntPLL;
begin
-------------------------------------------------------------------------------
-- Òàêòîâûé ãåíåðàòîð
-------------------------------------------------------------------------------
INT_CLK <= SPI_CLK;
--int_clk_tmp <= int_clk;
--oscill_inst : oscill PORT MAP (
-- oscena => RESET,
-- osc => INT_CLK
--);
-------------------------------------------------------------------------------
-- Ïðèåì áàéòà ïî øèíå SPI
-------------------------------------------------------------------------------
--dt_spi_tmp <= DT_SPI;
process(RESET, CE, SPI_CLK)
variable cntBit : integer range 7 downto 0;
variable DT_REG : std_logic_vector (7 downto 0);
variable fbstaf : boolean;
begin
-- Îòëàäêà

-- Îòëàäêà

if RESET = '0' or CE = '1' then
READY_DT_SPI <= '0';
DT_REG := x"00";
cntBit := 7;

fbstaf := false;
else
if falling_edge(SPI_CLK) then
DT_REG(cntBit) := MOSI;
if cntBit = 0 then
cntBit := 7;
if DT_REG /= x"7E" then
if fbstaf then
fbstaf := false;
DT_SPI <= DT_REG xor x"20";
else
DT_SPI <= DT_REG;
end if;
READY_DT_SPI <= '1';
else
fbstaf := true;
end if;
else
READY_DT_SPI <= '0';
cntBit := cntBit - 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Ðàçáîð ïðèíèìàåìûõ äàííûõ
-------------------------------------------------------------------------------
process(RESET, CE, READY_DT_SPI)

type tMode is (
Md_StartFlg, Md_Addr, Md_TypeCmd, Md_ChkCmd, Md_EndFlg, Md_Error
);
variable Mode : tMode;
variable Addr, TypeCmd : std_logic_vector (7 downto 0);
variable cntAtt : integer range 0 to 4;
variable i : integer;
-- PLL
variable NmbPLL : integer range -1 to 3;
variable cntPLLint : integer range 0 to 3;
variable NmbPLLtmp : integer range 0 to 3;
begin
if RESET = '0' or CE = '1' then
Mode := Md_StartFlg;
-- ATT
for i in 0 to 4 loop
fNewAT(i) <= false;
end loop;
-- RES
fNewPhRes <= false;
fNewResG1 <= false;
-- PLL
for i in 0 to 3 loop
fNewPLL(i) <= false;
end loop;
elsif falling_edge(READY_DT_SPI) then
-- Ðàçáîð ïðèíèìàåìûõ ñèìâîëîâ
case Mode is
when Md_StartFlg =>
if DT_SPI = x"7F" then
Mode := Md_Addr;
end if;
when Md_Addr =>
if DT_SPI = x"0A" then
Mode := Md_TypeCmd;
elsif DT_SPI /= x"7F" then
Mode := Md_StartFlg;
end if;
when Md_TypeCmd =>
Mode := Md_ChkCmd;
TypeCmd := DT_SPI;
-- Àòòåíþàòîðû
cntAtt := 0;
-- PLL
NmbPLL := -1;
when Md_ChkCmd =>
case TypeCmd is
-- Àòòåíþàòîðû
when x"01" =>
if DT_AT(cntAtt) /= DT_SPI(4 downto 0) then
fNewAT(cntAtt) <= true;
DT_AT(cntAtt) <= DT_SPI(4 downto 0);
end if;
-- Ñáðîñ
if cntAtt > 0 then
fNewAT(cntAtt - 1) <= false;
end if;
if cntAtt = 4 then
Mode := Md_EndFlg;
else
cntAtt := cntAtt + 1;
end if;
-- Ôàçîâûé ðåçèñòîð
when x"02" =>
Mode := Md_EndFlg;
fNewPhRes <= true;
DT_PhRes <= DT_SPI;
-- Ðåçèñòîð Ã1
when x"03" =>
Mode := Md_EndFlg;
fNewResG1 <= true;
DT_ResG1 <= DT_SPI;
-- PLL
when x"04" =>
if NmbPLL < 0 then
case DT_SPI(3 downto 0) is
when x"0" => NmbPLL := 0;
when x"1" => NmbPLL := 1;
when x"2" => NmbPLL := 2;
when x"3" => NmbPLL := 3;
when others =>
Mode := Md_Error;
end case;
cntPLLint := 0;
else
case cntPLLint is
when 0 =>
DT_PLL(NmbPLL)(23 downto 16) <= DT_SPI;
when 1 =>
DT_PLL(NmbPLL)(15 downto 8) <= DT_SPI;
when 2 =>
Mode := Md_EndFlg;
fNewPLL(NmbPLL) <= true;
DT_PLL(NmbPLL)(7 downto 0) <= DT_SPI;
when others =>
Mode := Md_EndFlg;
end case;
cntPLLint := cntPLLint + 1;
end if;
-- DDS
when x"06" =>
case cntDDS is
when 0 =>
DT_DDS(15 downto 8) <= DT_SPI;
when 1 =>
DT_DDS(7 downto 0) <= DT_SPI;
fNewDDS <= true;
Mode := Md_EndFlg;
when others =>
end case;

when others =>
Mode := Md_Error;
end case;
when Md_EndFlg =>
-- Àòòåíþàòîðû
fNewAT(4) <= false;
-- Ôàçîâûé ðåçèñòîð
fNewPhRes <= false;
-- PLL
fNewPLL(NmbPLL) <= false;
if DT_SPI = x"7F" then
Mode := Md_StartFlg;
else
Mode := Md_ChkCmd;
TypeCmd := DT_SPI;
end if;
when others =>
Mode := Md_StartFlg;
end case;
end if;
end process;
-------------------------------------------------------------------------------
-- Óñòàíîâêà PLL
-------------------------------------------------------------------------------
process(RESET, fNewPLL, fReadyPLL)
variable i : integer range 0 to 3;
begin
for i in 0 to 3 loop
if RESET = '0' then
fWrPLL(i) <= false;
elsif fNewPLL(i) then
fWrPLL(i) <= true;
elsif fReadyPLL(i) then
fWrPLL(i) <= false;
end if;
end loop;
end process;
process(RESET, INT_CLK)
type tcntPLLBit is array (0 to 3) of integer range 23 downto 0;

variable i : integer range 0 to 3;
variable cntPLLBit : tcntPLLBit;
begin
if RESET = '0' then
-- Óñòàîâêà øèíû PLL â èñõîäíîå ñîñòîÿíèå
for i in 0 to 3 loop
-- Ñèãíàëû
PLL_LE(i) <= '1';
PLL_DT(i) <= '0';
-- Ïåðåìåííûå
fReadyPLL(i) <= false;
cntPLLBit(i) := 0;
end loop;
elsif falling_edge(INT_CLK) then
-- PLL
for i in 0 to 3 loop
if fWrPLL(i) then
case cntPLL(i) is
when 0 =>
cntPLLBit(i) := 23;
PLL_LE(i) <= '0';
when 1 to 24 =>
PLL_DT(i) <= DT_PLL(i)(cntPLLBit(i));
cntPLLBit(i) := cntPLLBit(i) - 1;
when 25 =>
PLL_DT(i) <= '0';
when 26 =>
fReadyPLL(i) <= true;
PLL_LE(i) <= '1';
when others =>
fReadyPLL(i) <= true;
end case;
cntPLL(i) <= cntPLL(i) + 1;
else
cntPLL(i) <= 0;
fReadyPLL(i) <= false;
end if;
end loop;
end if;
end process;
process(cntPLL, INT_CLK)
variable i : integer range 0 to 3;
begin
for i in 0 to 3 loop
case cntPLL(i) is
when 2 to 25 =>
PLL_CLK(i) <= INT_CLK;
when others =>
PLL_CLK(i) <= '0';
end case;
end loop;
end process;
-------------------------------------------------------------------------------
-- Óñòàíîâêà ðåçèñòîðà Ã1
-------------------------------------------------------------------------------
process(RESET, fNewResG1, fReadyResG1)
begin
if RESET = '0' then
fWrResG1 <= false;
elsif fNewResG1 then
fWrResG1 <= true;
elsif fReadyResG1 then
fWrResG1 <= false;
end if;
end process;
process(RESET, INT_CLK)
variable cntResG1Bit : integer range 7 downto 0;
begin
if RESET = '0' then
-- Óñòàîâêà øèíû ðåçèñòîðà â èñõîäíîå ñîñòîÿíèå
DAC1_CS <= '1';
DAC1_DT <= '0';
--
cntResG1 <= 0;
elsif falling_edge(INT_CLK) then
-- Ðåçèñòîð Ã1
if fWrResG1 then
case cntResG1 is
when 0 =>
cntResG1Bit := 7;
DAC1_CS <= '0';
when 1 to 8 =>
DAC1_DT <= DT_ResG1(cntResG1Bit);
cntResG1Bit := cntResG1Bit - 1;
when 9 =>
DAC1_DT <= '0';
when 10 =>
fReadyResG1 <= true;
DAC1_CS <= '1';
when others =>
fReadyResG1 <= true;
end case;
cntResG1 <= cntResG1 + 1;
else
cntResG1 <= 0;
fReadyResG1 <= false;
end if;
end if;
end process;
process(cntResG1, INT_CLK)
begin
-- Ðåçèñòîð Ã1
case cntResG1 is
when 2 to 9 =>
DAC1_CLK <= INT_CLK;
when others =>
DAC1_CLK <= '0';
end case;
end process;
-------------------------------------------------------------------------------
-- Óñòàíîâêà ôàçîâîãî ðåçèñòîðà
-------------------------------------------------------------------------------
process(RESET, fNewPhRes, fReadyPhRes)
begin
if RESET = '0' then
fWrPhRes <= false;
elsif fNewPhRes then
fWrPhRes <= true;
elsif fReadyPhRes then
fWrPhRes <= false;
end if;
end process;
process(RESET, INT_CLK)
variable cntPhResBit : integer range 7 downto 0;
begin
if RESET = '0' then
-- Óñòàîâêà øèíû ôàçîâîãî ðåçèñòîðà â èñõîäíîå ñîñòîÿíèå
R1_CS <= '1';
R1_SD <= '0';
--
cntPhRes <= 0;
elsif falling_edge(INT_CLK) then
-- Ôàçîâûé ðåçèñòîð
if fWrPhRes then
case cntPhRes is
when 0 =>
cntPhResBit := 7;
R1_CS <= '0';
when 1 to 8 =>
R1_SD <= DT_PhRes(cntPhResBit);
cntPhResBit := cntPhResBit - 1;
when 9 =>
R1_SD <= '0';
when 10 =>
fReadyPhRes <= true;
R1_CS <= '1';
when others =>
fReadyPhRes <= true;
end case;
cntPhRes <= cntPhRes + 1;
else
cntPhRes <= 0;
fReadyPhRes <= false;
end if;
end if;
end process;
process(cntPhRes, INT_CLK)
begin
-- Ôàçîâûé ðåçèñòîð
case cntPhRes is
when 2 to 9 =>
R1_CLK <= INT_CLK;
when others =>
R1_CLK <= '0';
end case;
end process;
-------------------------------------------------------------------------------
-- Óñòàíîâêà àòòåíþàòîðîâ
-------------------------------------------------------------------------------
process(RESET, fNewAT, fReadyAT)
variable i : integer;
begin
for i in 0 to 4 loop
if RESET = '0' then
fWrAT(i) <= false;
elsif fNewAT(i) then
fWrAT(i) <= true;
elsif fReadyAT(i) then
fWrAT(i) <= false;
end if;
end loop;
end process;
process(RESET, INT_CLK)
type tcntATBit is array (0 to 4) of integer range 4 downto 0;

variable cntATBit : tcntATBit;
begin
if RESET = '0' then
-- Óñòàíîâêà àòòåíþàòîðîâ â èñõîäíîå ñîñòîÿíèå
AT1 <= ('0' & x"0");
AT1_LE <= '0';
AT2_LE <= '0';
AT3_LE <= '0';
AT4_LE <= '0';
AT5_LE <= '0';
for i in 0 to 4 loop
cntAT(i) <= 0;
end loop;
elsif falling_edge(INT_CLK) then
if fWrAT(0) then
AT1 <= DT_AT(0);
case cntAT(0) is
when 0 =>
AT1_LE <= '0';
when 1 =>
AT1_LE <= '1';
when 2 =>
AT1_LE <= '0';
fReadyAT(0) <= true;
when others =>
fReadyAT(0) <= true;
end case;
cntAT(0) <= cntAT(0) + 1;
else
cntAT(0) <= 0;
fReadyAT(0) <= false;
if fWrAT(4) then
AT1 <= DT_AT(4);
case cntAT(4) is
when 0 =>
AT5_LE <= '0';
when 1 =>
AT5_LE <= '1';
when 2 =>
AT5_LE <= '0';
fReadyAT(4) <= true;
when others =>
fReadyAT(4) <= true;
end case;
cntAT(4) <= cntAT(4) + 1;
else
cntAT(4) <= 0;
fReadyAT(4) <= false;
end if;
end if;
-- Àòòåíþàòîð 2
if fWrAT(1) then
case cntAT(1) is
when 0 =>
cntATBit(1) := 4;
when 1 to 3 =>
AT2_DT <= '0';
when 4 to 8 =>
AT2_DT <= DT_AT(1)(cntATBit(1));
cntATBit(1) := cntATBit(1) - 1;
when 9 =>
AT2_DT <= '0';
when 10 =>
AT2_LE <= '1';
when 11 =>
fReadyAT(1) <= true;
AT2_LE <= '0';
when others =>
fReadyAT(1) <= true;
end case;
cntAT(1) <= cntAT(1) + 1;
else
cntAT(1) <= 0;
fReadyAT(1) <= false;
end if;
-- Àòòåíþàòîð 3
if fWrAT(2) then
case cntAT(2) is
when 0 =>
cntATBit(2) := 4;
when 1 to 3 =>
AT3_DT <= '0';
when 4 to 8 =>
AT3_DT <= DT_AT(2)(cntATBit(2));
cntATBit(2) := cntATBit(2) - 1;
when 9 =>
AT3_DT <= '0';
when 10 =>
AT3_LE <= '1';
when 11 =>
fReadyAT(2) <= true;
AT3_LE <= '0';
when others =>
fReadyAT(2) <= true;
end case;
cntAT(2) <= cntAT(2) + 1;
else
cntAT(2) <= 0;
fReadyAT(2) <= false;
end if;
-- Àòòåíþàòîð 4
if fWrAT(3) then
case cntAT(3) is
when 0 =>
cntATBit(3) := 4;
when 1 to 3 =>
AT4_DT <= '0';
when 4 to 8 =>
AT4_DT <= DT_AT(3)(cntATBit(3));
cntATBit(3) := cntATBit(3) - 1;
when 9 =>
AT4_DT <= '0';
when 10 =>
AT4_LE <= '1';
when 11 =>
fReadyAT(3) <= true;
AT4_LE <= '0';
when others =>
fReadyAT(3) <= true;
end case;
cntAT(3) <= cntAT(3) + 1;
else
cntAT(3) <= 0;
fReadyAT(3) <= false;
end if;
end if;
end process;
process(cntAT, INT_CLK)
begin
-- Àòòåíþàòîð 2
case cntAT(1) is
when 2 to 9 =>
AT2_CLK <= INT_CLK;
when others =>
AT2_CLK <= '0';
end case;
-- Àòòåíþàòîð 3
case cntAT(2) is
when 2 to 9 =>
AT3_CLK <= INT_CLK;
when others =>
AT3_CLK <= '0';
end case;
-- Àòòåíþàòîð 4
case cntAT(3) is
when 2 to 9 =>
AT4_CLK <= INT_CLK;
when others =>
AT4_CLK <= '0';
end case;
end process;
end Arch_mng_pch;