@N: CD630 :"c:\Works\core_som\src\pll_cpu.vhd":5:7:5:13|Synthesizing core_som.pll_cpu.pll_cpu
@W: CD275 :"c:\Works\core_som\src\pll_cpu.vhd":22:10:22:12|Component declarations with different initial values are not supported. Port status of component dcm may have been given a different initial value in two different component declarations

library IEEE;
use IEEE.std_logic_1164.all; 
library VIRTEX2P;

entity pll_cpu is
  port(
       CLK_IN : in std_ulogic;
       FEEDBACK : in std_ulogic;
       RESET : in std_ulogic;
       LOCKED : out std_ulogic;
       PIN_OUT : out std_ulogic
  );
end pll_cpu;

architecture pll_cpu of pll_cpu is
component BUFG
  port (
       I : in std_ulogic;
       O : out std_ulogic
  );
end component;
component DCM
  generic(
       CLKDV_DIVIDE : REAL;
       CLKFX_DIVIDE : INTEGER;
       CLKFX_MULTIPLY : INTEGER;
       CLKIN_DIVIDE_BY_2 : BOOLEAN;
       CLKIN_PERIOD : REAL;
       CLKOUT_PHASE_SHIFT : STRING;
       CLK_FEEDBACK : STRING;
       DESKEW_ADJUST : STRING;
       DFS_FREQUENCY_MODE : STRING;
       DLL_FREQUENCY_MODE : STRING;
       DSS_MODE : STRING;
       DUTY_CYCLE_CORRECTION : BOOLEAN;
       FACTORY_JF : BIT_VECTOR;
       PHASE_SHIFT : INTEGER;
       STARTUP_WAIT : BOOLEAN
  );
  port (
       CLKFB:     in std_ulogic;
       CLKIN:     in std_ulogic;
       DSSEN:     in std_ulogic;
       PSCLK:     in std_ulogic;
       PSEN:      in std_ulogic;
       PSINCDEC:  in std_ulogic;
       RST:       in std_ulogic;
       CLK0:     out std_ulogic;
       CLK180:   out std_ulogic;
       CLK270:   out std_ulogic;
       CLK2X:    out std_ulogic;
       CLK2X180: out std_ulogic;
       CLK90:    out std_ulogic;
       CLKDV:    out std_ulogic;
       CLKFX:    out std_ulogic;
       CLKFX180: out std_ulogic;
       LOCKED:   out std_ulogic;
       PSDONE:   out std_ulogic;
       STATUS:   out STD_LOGIC_VECTOR(7 downto 0)
  );
end component;

signal NET345 : std_ulogic;
 begin
U1 : DCM    
  generic map(
       CLKDV_DIVIDE => 2.0,
       CLKFX_DIVIDE => 1,
       CLKFX_MULTIPLY => 4,
       CLKIN_DIVIDE_BY_2 => FALSE,
       CLKIN_PERIOD => 0.0,
       CLKOUT_PHASE_SHIFT => "NONE",
       CLK_FEEDBACK => "1X",
       DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
       DFS_FREQUENCY_MODE => "LOW",
       DLL_FREQUENCY_MODE => "LOW",
       DSS_MODE => "NONE",
       DUTY_CYCLE_CORRECTION => TRUE,
       FACTORY_JF => X"C080",
       PHASE_SHIFT => 0,
       STARTUP_WAIT => FALSE
  )
port map(       
        CLKFB=>     FEEDBACK,
        CLKIN=>     NET345,
        DSSEN=>     '0',
        PSCLK=>     '0',
        PSEN=>      '0',         
        PSINCDEC=>  '0',   
        RST=>       RESET,        
        CLK0=>      PIN_OUT,
        CLK90=>     OPEN,
        CLK180=>    OPEN,        
        CLK270=>    OPEN,     
        CLK2x=>     OPEN,   
        CLK2x180=>  OPEN,   
        CLKDV=>     OPEN,
        CLKFX=>     OPEN,     
        CLKFX180=>  OPEN,   
        STATUS=>    OPEN, 
        PSDONE=>    OPEN,
        LOCKED=>    LOCKED
  );

U2 : BUFG
  port map(
       I => CLK_IN,
       O => NET345
  );

end pll_cpu;