component DCM
generic(
CLKDV_DIVIDE : REAL := 2.0;
CLKFX_DIVIDE : INTEGER := 1;
CLKFX_MULTIPLY : INTEGER := 4;
CLKIN_DIVIDE_BY_2 : BOOLEAN := FALSE;
CLKIN_PERIOD : REAL := 0.0;
CLKOUT_PHASE_SHIFT : STRING := "NONE";
CLK_FEEDBACK : STRING := "1X";
DESKEW_ADJUST : STRING := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : STRING := "LOW";
DLL_FREQUENCY_MODE : STRING := "LOW";
DSS_MODE : STRING := "NONE";
DUTY_CYCLE_CORRECTION : BOOLEAN := TRUE;
FACTORY_JF : BIT_VECTOR := X"C080";
PHASE_SHIFT : INTEGER := 0;
STARTUP_WAIT : BOOLEAN := FALSE
);
port (
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0';
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out STD_LOGIC_VECTOR(7 downto 0) := "00000000"
);
end component;
signal NET345 : std_ulogic;
begin
U1 : DCM
port map(
CLKFB=> FEEDBACK,
CLKIN=> NET345,
DSSEN=> '0',
PSCLK=> '0',
PSEN=> '0',
PSINCDEC=> '0',
RST=> RESET,
CLK0=> PIN_OUT,
CLK90=> OPEN,
CLK180=> OPEN,
CLK270=> OPEN,
CLK2x=> OPEN,
CLK2x180=> OPEN,
CLKDV=> OPEN,
CLKFX=> OPEN,
CLKFX180=> OPEN,
STATUS=> OPEN,
PSDONE=> OPEN,
LOCKED=> LOCKED
);